(1) Field of the Invention
The invention relates to a method to determine a parameter of a damascene interconnect in an integrated circuit device and, more particularly, to a method to determine a parameter from a layout where the effects of dimension and local density, such as dishing, erosion, and optical proximity correction, are considered in the determination.
(2) Description of the Prior Art
As integrated circuit technology scales down, the impact of interconnect-induced delay becomes greater. That is, the parasitic resistance and capacitance (RC) of the interconnect system within the integrated circuit begins to play a greater role in the performance of the circuit. It is very important, therefore, that the parasitic RC components of the interconnect be modeled accurately.
Referring now to FIG. 1, a simplified top view of a partial, integrated circuit is shown. In this layout, two metal interconnect lines 18 and 19 are shown. Each line is formed in a common metal layer 10. Contact openings 14 are shown where each line 18 and 19 terminates at a coupling to an underlying element or interconnect, not shown. It is common in the art to use electronic design automation (EDA) to create these metal lines 18 and 19 to provide coupling between elements within a circuit layout.
EDA tools may be used to model the performance of the circuit or of sub-sections of the circuit. For example, simulators, such as SPICE, have long been used to model analog performance or critical timing paths in circuits. A simulator will use standard models for active circuit elements, such as MOS transistors. A network of active devices is linked in a netlist file such that the combined performance of the circuit components may be simulated. The effect of parasitic RC values in the interconnects between active elements is typically included if it is available.
EDA tools may be used to extract the parasitic RC values from the interconnect. Referring now to FIG. 2, the typical method 70 for determining the parasitic RC value is shown. First, the EDA tool analyzes the routing of one of the metal lines to extract the drawn dimensions in step 74. For example, the length and width of the metal routing 18 from point A to point B is measured from the layout data shown in FIG. 1. Referring again to FIG. 2, the drawn dimensions are then used to calculate the parasitic parameter, in this case the resistance, as shown. Note that the length (L) is divided by the width (W) to determine how many squares of the metal line are used in the routing. Next, the metal squares value is multiplied by a constant sheet resistance (PS) value to derive the resistance. The sheet resistance is ohms/square value that is a constant for a given metal level for the integrated circuit process as is well known in the art.
Referring now to FIG. 3, a cross sectional view of the aforementioned integrated circuit layout is illustrated. Each of the metal lines 18 and 19 is shown. Several dielectric layers 20, 24, and 30, are shown. In addition, an underlying metal layer 26 is shown. The parasitic impedance values for the metal lines 18 and 19 are based on several factors. First, the widths (W1 and W2) of each line 18 and 19 are important. Typically, widths of features, such as metal lines, are carefully controlled by monitoring critical dimension (CD) structures that are on the included on each IC. Further, the widths W1 and W2 of metal lines 18 and 19 in the same metal layer 10 are controlled by the drawn dimensions. Second, the depths D1 and D2 of the metal lines 18 and 19 are important. It is not typically possible to monitor interconnect thickness using a CD technique. However, the combination of the width W1 and the thickness D1 of the metal line is important because the actual resistivity of the metal line is directly proportional to the cross sectional area defined by the width multiplied by the depth. The third important factor is the distance D3 between the top of the underlying metal line 26 and the metal line 18 under analysis. The amount of capacitive coupling between overlying metal lines depends directly on the distance D3 between these lines. A fourth important factor is the spacing (S1) between adjacent metal lines 18 and 19. The capacitive coupling between these lines 18 and 19 depends on this spacing.
In a typical EDA analysis of an integrated circuit layout, the tool makes several assumptions. First, the drawn dimensions W1 and W2 are equally effected by the manufacturing process. If the manufacturing process causes the width dimension of a metal line to increase or to decrease, then this increase or decrease amount will be consistent for all of the metal lines. For example, a drawn width W1 of line 18 is 0.5 microns. After processing, the actual CD value is measured at 0.45 microns. It is assumed that the width W2 of another metal line 19 in the same metal layer 10 will likewise lose 0.05 microns from the drawn dimension to the physical value. The EDA tool may add a positive or negative bias amount to the drawn dimensions to account for the process effect. However, this is done globally for all of the metal lines of the layer. The EDA extraction tool also assumes that all of the metal lines 18 and 19 in a metal layer 10 have the same depth or thickness such that D1=D2. Finally, the EDA tool assumes that the depth or distance D3 between metal levels 10 and 26 is a constant value.
By using the above stated assumptions, the EDA tool can determine the parasitic RC parameters by simply extracting the drawn dimensions and then multiplying the results by constant per unit values of sheet resistance (ohms/square) or of capacitance (Farads/cm2). However, the assumption of uniformity may not be valid.
Referring now to FIG. 4, a cross section of an integrated circuit device is shown. Two metal lines 34 and 36 are formed in a common metal layer 10. In this case, a first metal line 34 is designed to a much larger width than the than the second metal line 36. In this case, the metal lines 34 and 36 are formed using a damascene process. In a damascene process, interconnect lines are formed by etching trenches in the dielectric layer 20, depositing metal 10, and then polishing down the metal to define the metal lines 34 and 36. Damascene processes are particularly useful for forming copper-based interconnects since difficult copper etching is avoided.
In the cross section, a copper dishing effect is shown on one of the metal lines 34. Dishing occurs when the chemical mechanical polishing (CMP) operation removes excessive copper on a metal line 34 to cause a dish shaped profile. Generally, dishing occurs on relatively wide metal lines 34 where the selectivity of the CMP process to copper causes the copper removal rate to be accelerated. Of particular importance to the present invention is the fact that the depth or thickness D1 of the metal line 34 is affected. The dishing effect causes the thickness D1 of the large metal line 34 to be significantly less than the thickness D2 of the small metal line 36. The uniform thickness assumption is violated. An EDA tool that determines the resistivity using a constant resistivity value, based on the standard thickness D2, will understate the resistance value of the first metal line 34.
Referring now to FIG. 5, a second problem situation is shown. In this case, an array of closely-spaced metal lines 40 is formed in one area of the integrated circuit while a single metal line 42 is formed in another area. All of the lines 40 and 42 are drawn to the same dimension in the layout. However, the single line 42 exhibits a smaller physical width W2 than the width W1 of the closely-spaced lines 40. The difference in line sizes is due to optical proximity correction (OPC). To define the line trenches in the dielectric layer 20, a photoresist layer, not shown, is exposed to light through an optical mask. Adjacent features on the mask can create light interference that is transferred onto the photoresist pattern. It is found that closely-spaced features will tend to be over-exposed. For this reason, the closely-spaced trench lines 40 may be etched to a larger size than a single trench 42. Some type of biasing technique may be used to correct for overetched line sizes. However, this biasing is performed globally across the entire circuit. Therefore, it is found that OPC will cause significant differences in the physical dimensions of the same-dimensioned, final damascene lines due to variation in the local density of features. This variation in physical widths W1 and W2 will cause the standard EDA parameter extraction to be in error.
Referring now to FIG. 6, a third problem situation is shown. Again, a dense array of metal lines 50 are formed in one area of the device while a single metal line 52 is formed in another area. In this case, an erosion effect may occur in the closely-spaced, metal line region 50. In the erosion effect, significant dielectric layer 20 is lost. The resulting damascene metal lines 50 have a reduced thickness D1 when compared to the thickness D2 of the single metal line 52. If the EDA tool uses a constant value for the resistivity of the metal lines, then the results will be significantly in error.
Several prior art inventions relate to methods to extract parasitic impedance values from integrated circuit layouts. U.S. Pat. No. 6,381,730 B1 to Chang et al describes a parasitic extraction tool for use on an integrated circuit design. For a selected interconnect, parasitic impedance values, such as inductance, are extracted from the layout using an interconnect primitive library. U.S. Pat. No. 6,312,963 B1 to Chou et al discloses a method to derive estimates of physical interconnect process parameters from an IC layout. Test structures are fabricated and measured to determine values within a range of physical interconnect parameters. Scanning electron microscope measurements may also be used to derive parameters. This method discloses characterization of systematic variation of interconnect process parameters, such as line width and dielectric thickness. A line width, correction factor is a function of line width and space. An electric field solver method is used. U.S. Pat. No. 6,243,653 to Findley describes a parasitic parameter extraction method for use in an IC layout. Extraction of parasitic effects due to metal or polysilicon fill structures is described.